1. Field of the Invention
This invention relates to a plasma display panel, and more particularly to a method and apparatus of driving a plasma display panel that is adaptive for preventing a damage of a driving integrated circuit caused by an abnormal discharge generated from a non-display area.
2. Description of the Related Art
Generally, a plasma display panel (PDP) excites and radiates a phosphorus material using an ultraviolet ray generated upon discharge of an inactive mixture gas such as He+Xe, Ne+Xe or He+Ne+Xe, to thereby display a picture. Such a PDP is easy to be made into a thin-film and large-dimension type. Moreover, the PDP provides a very improved picture quality owing to a recent technical development.
Referring to FIG. 1, a discharge cell of a conventional three-electrode, AC surface-discharge PDP includes a sustain electrode pair having a scan electrode Y and a sustain electrode Z provided on an upper substrate 1, and an address electrode X provided on a lower substrate 2 in such a manner to perpendicularly cross the sustain electrode pair. Each of the scan electrode Y and the sustain electrode Z consists of a transparent electrode, and a metal bus electrode thereon. On the upper substrate 1 provided with the scan electrode Y and the sustain electrode, an upper dielectric layer 6 and a MgO protective layer 7 are disposed. A lower dielectric layer 4 is formed on the lower substrate 2 provided with the address electrode X in such a manner to cover the address electrode X. Barrier ribs 3 are vertically formed on the lower dielectric layer 4. A phosphorous material 5 is provided on the surfaces of the lower dielectric layer 4 and the barrier ribs 3. An inactive mixture gas such as He+Xe, Ne+Xe or He+Ne+Xe is injected into a discharge space among the upper substrate 1, the lower substrate 2 and the barrier ribs 3. The upper substrate 1 is joined with the lower substrate 2 with the aid of a sealant (not shown).
Such a PDP makes a time-divisional driving of one frame, which is divided into various sub-fields having a different emission frequency, so as to realize gray levels of a picture. Each sub-field is again divided into an initialization period (or reset period) for initializing the entire field, an address period for selecting the scan line and selecting the cell from the selected scan line and a sustain period for expressing gray levels depending on the discharge frequency. The initialization period is divided into a set-up interval supplied with a rising ramp waveform and a set-down interval supplied with a falling ramp waveform. For instance, when it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60 second (i.e. 16.67 msec) is divided into 8 sub-fields SF1 to SF8 as shown in FIG. 2. Each of the 8 sub-field SF1 to SF8 is divided into an initialization period, an address period and a sustain period as mentioned above. Herein, the initialization period and the address period of each sub-field are equal for each sub-field, whereas the sustain period and the number of sustain pulses assigned thereto are increased at a ratio of 2n (wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field.
FIG. 3 shows a driving waveform of the conventional PDP shown in FIG. 1.
Referring to FIG. 3, the PDP is divided into an initialization period for initializing the full field, an address period for selecting a cell, and a sustain period for sustaining a discharge of the selected cell for its driving.
In the initialization period, a rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in a set-up interval SU. A discharge is generated within the cells at the full field with the aid of the rising ramp waveform Ramp-up. By this set-up discharge, positive wall charges are accumulated onto the address electrode X and the sustain electrode Z while negative wall charges are accumulated onto the scan electrode Y. In a set-down interval SD, a falling ramp waveform Ramp-down falling from a positive voltage lower than a peak voltage of the rising ramp waveform Ramp-up is simultaneously applied to the scan electrodes Y after the rising ramp waveform Ramp-up was applied. The falling ramp waveform Ramp-down causes a weak erasure discharge within the cells to erase a portion of excessively formed wall charges. Wall charges enough to generate a stable address discharge are uniformly left within the cells with the aid of the set-down discharge.
In the address period, a negative scanning pulse scan is sequentially applied to the scan electrodes Y and, at the same time, a positive data pulse data is applied to the address electrodes X in synchronization with the scanning pulse scan. A voltage difference between the scanning pulse scan and the data pulse data is added to a wall voltage generated in the initialization period to thereby generate an address discharge within the cells supplied with the data pulse data. Wall charges enough to cause a discharge when a sustain voltage is applied are formed within the cells selected by the address discharge.
Meanwhile, a positive direct current voltage Zdc is applied to the sustain electrodes Z during the set-down interval and the address period. The direct current voltage Zdc establishes a voltage difference between the sustain electrode Z and the scan electrode Y or between the sustain electrode Z and the address electrode X such that a set-down discharge is generated between the sustain electrode Z and the scan electrode Y in the set-down interval and a discharge is not largely generated between the scan electrode Y and the sustain electrode Z in the address period.
In the sustain period, a sustaining pulse sus is alternately applied to scan electrodes Y and the sustain electrodes Z. Then, a wall voltage within the cell selected by the address discharge is added to the sustain pulse sus to thereby generate a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied. Just after the sustain discharge was finished, a ramp waveform ramp-ers having a small pulse width and a low voltage level is applied to the sustain electrode Z to thereby erase wall charges left within the cells of the entire field.
Meanwhile, as shown in FIG. 4 and FIG. 5, the PDP includes a discharge space having the same structure as the discharge cell of the active area 31 at each of an upper non-display area 32 positioned at the upper outside of the active area 31 and a lower non-display area 33 positioned at the lower outside thereof. In other words, each of the upper non-display area 32 and the lower non-display area 33 is provided with an address electrode X, upper/lower Y dummy electrodes UY1, UY2, BY1 and BY2, and upper/lower Z dummy electrodes UZ1, UZ2, BZ1 and BZ2, and dielectric layers 4 and 6 are formed in such a manner to cover the electrodes X, UY1, UY2, BY1, BY2, UZ1, UZ2, BZ1 and BZ2.
The dummy electrodes UDE and BDE provided at each of the upper non-display area 32 and the lower non-display area 33 cause a discharge at the non-display area upon aging process, to thereby stabilize discharge characteristics of discharge cells on the first horizontal line and the nth horizontal line of the active area 31 at the same condition as other discharge cells at the active area 31. To this end, a voltage capable of causing a discharge upon aging process is applied to the dummy electrodes UDE and BDE while a voltage is not applied thereto after the aging process.
However, the conventional PDP has a problem in that a discharge is accidentally generated from the upper non-display area 32 and the lower non-display area 33. Such a discharge is referred to as “abnormal discharge”. More specifically, if a discharge such as an initialization discharge, an address discharge and a sustain discharge, etc. occurs upon driving of the PDP, then space charges generated by the discharge are accumulated onto dielectric layers of the upper non-display area 32 and the lower non-display area 33. For instance, upon address discharge, while a negative scan pulse scan being sequentially shifted into the scan electrodes Y1 to Yn as shown in FIG. 5, positive space charges 53 are moved into the lower non-display area 33 and, at the same time, negative space charges 51 are moved into the upper non-display area 32. The space charges 51 and 53 moved into the non-display areas 32 and 33 in this manner are accumulated within the non-display areas 32 and 33, or onto the dielectric layers 4 and 6 having covered electrodes at the active area adjacent to the non-display areas 32 and 33. If a wall charge 61 of the discharge space rising by wall charges accumulated on the non-display areas 32 and 33 and the active area 31 adjacent thereto becomes more than a voltage enough to cause a discharge as shown in FIG. 6, then an abnormal discharge accidentally occurs within the non-display areas 32 and 33 and the active area 31 adjacent thereto.
Due to this abnormal discharge, a visible light 48 generated from the non-display areas 32 and 33 or the upper/lower edges of the active area 31 adjacent thereto is viewed by an observer as shown in FIG. 7. In the worse case, the PDP cannot display a picture during several seconds and its discharge cells may be damaged due to the abnormal discharge.
In order to solve such a problem, the upper/lower dummy Y electrodes UY1, UY2, BY1 and BY2 shown in FIG. 8 are kept at a floating state while the upper/lower dummy Z electrodes UZ1, UZ2, BZ1 and BZ2 are supplied with a predetermined driving voltage via the voltage supplier 40. Accordingly, wall charges within the non-display areas 32 and 33 can be reduced. Further, a movement of the wall charges can be restrained to prevent an abnormal discharge within the non-display areas 32 and 33.
However, since the upper/lower dummy Y electrodes UY1, UY2, BY1 and BY2 have been kept at a floating state, a locally serious accumulation of wall charges are generated. When the wall charges are enlarged in such a manner to be leaded to an abnormal discharge type, integrated circuits (IC's) around the wall charges causes defects identical to a case where a driving waveform is applied thereto.
In order to overcome this problem, as shown in FIG. 9, a second driving voltage, for example, a driving voltage supplied to the Y electrode of the active area during the initialization period is applied, via a second voltage supplier 42 to the upper/lower dummy Y electrodes UY1, UY2, BY1 and BY2 while a first driving voltage, for example, a driving voltage supplied to the Z electrode of the active area during the initialization period is applied, via a first voltage supplier 40 to the upper/lower dummy Z electrodes UZ1, UZ2, BZ1 and BZ2. Accordingly, wall charges within the non-display areas 32 and 33 can be reduced. Further, a movement of the wall charges can be restrained to prevent an abnormal discharge within the non-display areas 32 and 33.
However, the PDP having the upper/lower dummy Y electrodes UY1, UY2, BY1 and BY2 connected to the second voltage supplier 42 as shown in FIG. 9 has a problem in that an abnormal current, for example, a current of about 700 mA is applied from the second voltage supplier 42 to the dummy Y electrodes UY1, UY2, BY1 and BY2 to thereby cause an abnormal discharge, and this discharge current is reversely flown into the data driving IC and the scan driving IC having a chip on film (COF) type to thereby damage the driving IC's.